1. Field of the Invention
The present invention relates generally to electrostatic discharge (ESD) protection in integrated circuit (IC) packages, and more particularly, to ESD protective devices provided to selected no-connect pins on an IC package for protection of the IC package and internal circuits against ESD stress applied to the no-connect pin.
2. Background Art
Electrostatic discharge (ESD) is a movement of static electricity from a nonconductive surface, which could cause damage to semiconductors and other circuit components in ICs. A person walking on a carpet, for instance, can carry an amount of electrostatic charge up to several thousands of volts under high humidity conditions and over 10,000 volts under low humidity conditions. When touching ICs by hand, the instantaneous power level of the ESD could cause severe damage to the ICs. CMOS (complementary metal-oxide semiconductor) logic ICs are especially vulnerable to ESD.
To protect IC packages against ESD damage, various solutions have been proposed. One solution suggests the provision of an ESD protective device between the internal semiconductor devices in the IC chip (hereinafter referred to as "internal circuit") and the corresponding bonding pad. FIG. 1 shows the wire connection in an IC package which includes bonding pads 11, 13, 15 electrically connected to the internal circuit 20 of the IC package. A number of pins, or leads, for example, as those indicated by the reference numerals 10, 12, 14, 16, 17, 18, 19 are provided on the IC package, of which the pin 10 is a power pin (i.e., Vdd or Vss pin) which is connected to the bonding pad 11 via a bonding wire 100, pin 12 is an I/O pin internally connected to the bonding pad 13 via bonding wire 120, pin 14 is an input pin internally connected to the bonding pad 15 via bonding wire 140, and other pins 16, 17, 18, 19 are not in use and are thus referred to as no-connect pins. To prevent ESD current from flowing into the internal circuit via pins 10, 12, 14, conventional ESD protective circuits (not shown) are provided between the bonding pads 11, 13, 15 and the internal circuit so as to divert the ESD current from entering the internal circuit.
A trend in IC packaging is to provide a larger number of pins with a smaller pitch between the pins to achieve a high packing density of I/O on the IC package. Thus, the gap (i.e., the pitch) between two adjacent pins, for example, as indicated by the reference number G in FIG. 1 between the pins 14 and 19, is reduced. This, however, causes new problems in providing ESD protection for the IC package, as discussed in detail in a paper entitled "New Failure Mechanism due to No-Connect Pin ESD Stressing" by Matsumoto of Japan in 1994 EOS/ESD Symposium, pp.90-95. The paper reveals the fact that, when a human body model (HBM) ESD pulse is repeatedly applied to a no-connect pin on the IC package, any of the two neighboring pins, if wired to the internal circuit, would become vulnerable to ESD damage. This is because the electrostatic charge will accumulate in the resin around the no-connect pin, resulting in a large potential difference between the no-connect pin and its neighboring pins, which would significantly reduce the ESD resistance capability of the neighboring pins.
Taking the IC package of FIG. 1 as an example, it will be assumed that the input pin 14 is able to withstand a maximum ESD voltage of 3 kV when applied directly to the input pin 14. When an ESD voltage of 1.5 kV, for example, is received by the no-connect pin 19, the electrostatic charge will be accumulated in the resin around the no-connect pin 19, resulting in a large potential difference between the no-connect pin to its neighboring pins that would eventually cause an electrostatic discharge through the gap G to the neighboring wired pin 14, thus causing ESD damage to the internal circuit 20 via the bonding wire 140 and the bonding pad 15. Therefore, it is apparent that an ESD voltage having a significantly smaller magnitude than the maximum level withstandable by the wired pins, when received by a neighboring no-connect pins, could nonetheless cause ESD damage to the IC via the wired pins.
Accordingly, there remains a need for schemes of positioning ESD protective devices that are capable of protecting the wired pins against ESD due to ESD voltages received by neighboring no-connect pins.